Transistors that are more energy-efficient are essential for the development of increasingly powerful mobile devices and of higher performance computers. The constant decrease in the size of transistors and the increase in packing density of over 109 transistors per chip brings about energy consumption that is too high and, as a result, a problematic generation of heat. Although conventional field-effect transistors (MOSFETs) are constantly being improved and energy consumption also reduced as a result, the switching behavior limits energy efficiency in principle. This is to do with the thermally distributed energy distribution at ambient temperature of the charge carriers injected into the transistor channel. The switching behavior can be described by the “inverse subthreshold slope” (S), which states by how many millivolts (mV) the gate voltage must be increased in order to increase the output current (Ion) by a decade (dec). At ambient temperature, this results in a minimum S of 60 mV/dec. In the case of short-channel transistors, such as those used in high performance processors, short-channel effects increase S to about 100 mV/dec at a gate length of 32 nm. These basic limits also increase the off current (Ioff) at a given threshold voltage, and therefore increase the losses too.
In order to reduce the energy consumption of transistors, the operating voltage (=drain voltage (Vdd)) and the inverse subthreshold slope (S) should be reduced. The dynamic energy consumption is scaled by the square of Vdd; if the switching frequency is also taken into account, it is even scaled by the cube of Vdd. A reduction in S allows a reduction in the threshold voltage without a substantial rise in Ioff.
In order to meet these requirements, a new kind of switch element known as a “steep slope device” is required. The most promising concepts include “band-to-band tunneling (BTBT) transistors”, referred to here as tunnel FETs (TFET), and MOSFETs having an upstream energy filter. The latter have not yet been achieved owing to enormous technological problems. Tunnel field-effect transistors produced to date have generally not met expectations yet since the output currents are too small and S is only in a non-usable low gate voltage range of <60 mV/dec.
FIG. 1 schematically illustrates the switching behavior of a conventional MOSFET and of a tunnel field-effect transistor. The transfer characteristic of the current on the drain side (Id) is shown against the gate voltage. The dashed line shows the minimum inverse subthreshold slope S for MOSFETs at 60 mV/dec. Vt denotes the threshold voltage. According to simulation calculations, tunnel field-effect transistors can achieve S<60 mV/dec. Moreover, the tunnel field-effect transistor can already be fully switched on at much lower gate voltages. As a result, the threshold voltage Vt can be reduced in comparison to MOSFETs (owing to the lower S) without increasing Ioff, and therefore higher energy efficiency can be achieved.
FIG. 2 shows the basic construction of a planar tunnel field-effect transistor consisting of a source-channel-drain structure, for example a p-i-n structure, having a gate arrangement 203, 204, the gate arrangement advantageously comprising a gate dielectric 203 having high permittivity (k), such as HfO2. The gate contact (gate electrode) 204 is achieved with the aid of a metal layer (for example, TiN). The source 206 and drain 205 are interchangeable in the case of transistors having a symmetrical construction. The tunnel junction 202 can be achieved either on the source side or on the drain side. 201 indicates intrinsic silicon.
For the purpose of simplification, the tunnel junction at the source-to-channel junction is selected for this prior art. The transistor is reverse-biased, so for a p-TFET the n+-doped source is set at V=0 and a negative voltage is applied at the p+-doped drain and the gate. Similarly, for an n-TFET, the polarity of the source and drain and of the drain and gate voltage are interchanged. As a result, the conduction and valence band is normally increased in the channel and drain region. When voltages are sufficiently high, an electronic band profile is produced in which the minority charge carriers (in this case, holes) tunnel from the conduction band of the source into the valence band of the channel material. The tunnel probability TWKB according to the WKB approximation is given by:
      T    WKB    ≈      exp    ⁡          (              -                              4            ⁢            Λ            ⁢                                          2                ⁢                                                                  ⁢                m                *                                      ⁢                          E              g                              3                /                2                                                          3            ⁢                                                  ⁢            q            ⁢                                                  ⁢                          ℏ              ⁡                              (                                  ΔΦ                  +                                      E                    g                                                  )                                                        )      
In the equation, Λ denotes the natural length, m* the effective mass of the charge carriers, Eg the band gap, ΔΦ the potential difference between the valence band lower edge in the channel and the conduction band upper edge in the source, q the electron charge and h the Planck constant divided by 2π. The natural length Λ is the sum of Λg and Λch. The first summand Λg is a measurement for the electrostatic control of the transistor by the gate; the second summand Λct, describes the steepness of the tunnel junction.
The field dependency of the tunnel current is given by the Kane model. Accordingly, band-to-band tunneling increases exponentially with the electrical field at the tunnel junction. Using simulation calculations, it was calculated that fringing fields starting from a gate dielectric having very high permittivity lead to better characteristics.
L. Knoll, Q. T. Zhao, Lars Knoll, A. Nichau, S. Trellenkamp, S. Richter, A. Schäfer, D. Esseni, Selmi, K. K. Bourdelle, S. Mantl, “Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors”, IEEE ELECTRON DEVICE LETTERS vol. 34, no. 6, pp. 813-815, 2013. Nanowire band-to-band tunnel field-effect transistors achieved to date demonstrated inverse subthreshold slopes S of less than 60 mV/dec, which are largely attributable to the improved steepness of the tunnel junction owing to the use of a silicided source region having subsequent dopant segregation, only in the case of very low drain currents.
TFETs have also been proposed and produced having semiconductors that have smaller band gaps. A simulation for a planar TFET having silicon germanium (Si—Ge) has become known from K. Bhuwalka et al. (P-Channel Tunnel Field Effect Transistors down to Sub-50 nm Channel Length” Jap. J. of Appl. Physics 45 (2006) pages 3106-3109), with which the benefit of the smaller band gap could be proven. Experimental results from M. Schmidt, R. A. Minamisawa, S. Richter, R. Luptak, J.-M. Hartmann, D. Buca, Q. T. Zhao and S. Mantl “Impact of strain and Ge concentration on the performance of planar SiGe band-to-band-tunneling transistors”, Proc. of ULIS 2011 Conference, confirm this benefit, albeit with S>60 mV/dec. In this approach, source, channel and drain made from a SiGe alloy having a Ge content of 30-65 at. % were investigated.
Vertical In0.53Ga0.47As0.47 band-to-band tunnel field-effect transistors disadvantageously have not delivered the expected results to date either.
A more in-depth approach by C. Hu “Green Transistor as a solution to the IC Power Crisis”, Proc. of ICSICT Conference, Peking, 2008 (978-1-4244-22186-2/08 @2008 IEEE), uses a complicated heterostructure, in which a thin layer of n+-doped strained silicon is placed on p+-doped Ge below the gate on the source side about as far as to the center of the gate of the transistor. This results in a tunnel junction consisting of p+—Ge/n+-strained silicon. This approach has the aforementioned advantages of the integration of a material having smaller band gaps in the tunnel region, and also the surface of the tunnel junction is enlarged as a result of the integration below the gate. A big disadvantage of this concept is the difficult implementation, which has prevented it from being achieved to date.
Even the proposal by Bhuwalka et al. (Proc. ESSDERC 2004, 0-7803-8478-4/04@2004 IEEE) of introducing an ultrathin SiGe delta layer having sharp boundaries at the tunnel junction in order to improve the tunnel current only leads to small improvements.
The production of a TFET in which the tunnel junction extends in parallel with the electric field of the gate is known from U.S. Pat. No. 8,258,031 B2. The vertical tunnel junction having a counter-doped pocket increases the tunnel cross-sectional area and therefore the tunnel current. The production method starts in this case with a silicon on insulator (SOI) layer. The highly-doped tunnel junction is obtained by selective growth, which can disadvantageously generate a tunnel boundary having a higher defect density. This in turn leads to a tunnel process across these defects and therefore to a large inverse subthreshold slope (S).
The publication by Kanghoon Jeon, Wei-Yip Loh, Pratik Patel, Chang Yong Kang, Jungwoo Oh, Anupama Bowonder, Chanro Park, C. S. Park, Casey Smith, Prashant Majhi, Hsing-Huang Tseng, Raj Jammy, Tsu-Jae King Liu, and Chenming Hu, “Si Tunnel Transistors with a Novel Silicided Source and 46 mV/dec Swing”, 2010 Symposium an VLSI Technology Digest of Technical Papers, page 121-122) reports on TFETs having a homojunction, which have a source region silicided with NiSi. The special shape of the edges of the silicided region is not reproducible, however, if the thickness or width of the silicon layer is varied.